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61003107
- 公 共 电 话 通 话 计 费 系 统 在本课程中所选择的课题是用Verilog HDL实现的公共电话。该公共电话所实现的功能有打电话、修改密码。 公共电话共包括以下几个状态：挂机、待机、身份确认、修改密码、通话等五个状态。-The pay phone converses to charge system In this course the topic chosen is use Verilog HDL carry out of pay phone.The function carri
telephone
- 利用verilog语言设计公共电话共包括以下几个状态：挂机、待机、身份确认、修改密码、通话等五个状态。内含详细的源码以及设计过程、模块-The use of public telephones were verilog language design include the following states: hang up, standby, identification, change passwords, call the five states. Includes a detailed
traffic_control
- 使用verilog语言编写的双向交通信号控制灯程序，通过状态机转换实现车行道和人行道功能，以cyclone IV系列开发板做为应用平台。-Verilog language using two-way traffic signal control lights procedures, driveway and sidewalk functions via a state machine transition to cyclone IV Series development board as the
VendingMac
- Verilog实现的自动售货机，使用有限状态机进行处理。包括Modelsim和Spnplify的综合工程。-Verilog realize vending machines, using a finite state machine for processing. Including integrated engineering and Spnplify of Modelsim.
zhuangtaiji
- verilog一个有趣的状态机事例，简单易懂。适用于初学者。是一个小游戏的，sparten板子可用。 内含测试。-Verilog an interesting state machine case, simple and easy to understand. Suitable for beginners. Is a small game, sparten board available. Inclusion test.
waterlights_fsm
- 采用Verilog语言，编写三段式状态机，实现流水灯操作，已测试验证通过-Using Verilog language, written in three-state machine to achieve water lights operating, it has been verified by test
FSM
- Verilog编写的FPGA有限状态机一段式描述。-The FSM of FPGA based on Verilog.
loveyou
- Verilog实现love you 状态机的小例子-a small example of the realization of the love you state machine with Verilog
FPGA_SDRAM
- UART作为RS232协议的控制接口得到了广泛的应用，将UART的功能集成在FPGA芯片中，可使整个系统更为灵活、紧凑，减小整个电路的体积，提高系统的可靠性和稳定性。提出了一种基于FPGA的UART的实现方法，具体描述了发送、接收等模块的设计，恰当使用了有限状态机，实现了FPGA片上UART的设计，给出了仿真结果。-fpga verilog uart sram
RISC_CPU
- RISC_CPU 设计练习这是用verilog写的一个基于状态机的简易RISC_CPU的设计，里面包含各个模块，每个模块经过仿真没有问题，整个工程在板子上经过试验。--This is a verilog to write a simple RISC_CPU based state machine design, which contains various modules, each module through simulation without problems, the whole pr
FPGA_Project
- USB 2.0的数据传输verilog程序，采用的是slave状态机实现其功能。其中包括读、写功能 -USB 2.0 data transfer verilog program, using the slave state machine functionality. Including reading and writing functions
sequence_detector
- verilog之序列检测，vivado工程，使用状态机的方式检测任意长度的数据顺序，提供四个检测工程，并全部带有Testbench,保证你能方便的学会序列检测这个知识点。-Data in a sequential manner to detect any length of sequence detection verilog, vivado engineering, using a state machine provides four detection project, and all w
StateMachine
- VERILOG语言，ISE13.4实现的步进电梯的状态机，可以仿真。-VERILOG language, ISE13.4 achieve step elevator state machine can be simulated.
CIC_verilog
- 采用verilog实现的三级CIC抽取器，输入8位数据，输出26位数据，使用有限状态机用于实现下采样，包括积分器实现模块和梳状器实现模块-Using verilog to achieve three CIC decimation filter, the input 8-bit data output 26-bit data, the use of finite state machines for sampling, including the integrator and comb to im
state_led_one
- 基于verilog HDL的状态机8位流水灯（一个按键控制左转和右转），开发环境Diamond 3.7(64-bit)；FPGA采用LCMXO2-1200HC-4MG132C；时钟25M；开发板：与非网小脚丫-Based verilog HDL state machine eight light water (a key control buttons turn left and turn right), the development environment Diamond 3.7 (64-b
SDRAM
- sdram 状态机驱动源程序工程 完全使用verilog hdl写的-sdram state machine driver source project written entirely in verilog hdl
FSW
- verilog写的有限状态机（FSW）序列检测，检测到0100_01给出高电平，包含测试文件，Modelsim下仿真成功。-Verilog written finite state machine( FSW) sequence detection, detected 0100_01 given high, including the test file, Modelsim simulation success.
project2
- 关于verilog有限状态机的设计，可以供初学者对有限状态机的设计有初步了解-About verilog finite state machine design, finite state machine for beginners to have a preliminary understanding of the design
soda_machine_mealyamoore
- soda_machine的一个有限状态机，用verilog描述，分别有moore和mealy,还提供了testbench.-soda_machine of a finite state machine, with verilog descr iption, respectively, moore and mealy, also provides a testbench.
iic_ctrl
- 基于Verilog的IIC接口，使用状态机实现，可以支持速率参数化。-implement IIC master controller by using Verilog language.